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datasheet 12-output low power differential buffer for pcie gen3 and qpi 9ZXL1230 idt? 12-output low power differential buffer for pcie gen3 and qpi 1 9ZXL1230 rev b 041112 general description the 9ZXL1230 is a small-footprint, low power 12-output differential buffer that meets all the performance requirements of the intel db1900z specification. it is pin compatible to the 9zx21200. the 9ZXL1230 is backwards compatible to pcie gen2 and qpi 6.4gt/s specifications. a fixed, internal feedback path maintains low drift for critical qpi applications. recommended application 12-output low power pcie gen3/qpi differential buffer for romley output features ? 12 - 0.7v low-power hcsl-compatible output pairs features/benefits ? low-power push-pull outputs; save power and board space - no rp ? pin compatible to 9zx21200; easy path to >50% power savings ? space-saving 56-pin qfn package ? fixed feedback path for 0ps input-to-output delay ? 9 selectable smbus addresses; mulitple devices can share the same smbus segment ? 4 oe# pins; hardware control of four outputs, other outputs free run ? pll or bypass mode; pll can dejitter incoming clock ? 100mhz or 133mhz pll mode operation; supports pcie and qpi applications ? selectable pll bandwidth; minimizes jitter peaking in downstream pll's ? spread spectrum compatible; tracks spreading input clock for low emi key specifications ? cycle-to-cycle jitter <50ps ? output-to-output skew <65 ps ? input-to-output delay variation <50ps ? pcie gen3 phase jitter <1.0ps rms ? qpi 9.6gt/s 12ui phase jitter <0.2ps rms block diagram logic dif(11:0) hibw_bypm_lobw# smbdat smbclk ckpwrgd/pd# smb_a0_tri smb_a1_tri 100m_133m# z-pll (ss compatible) dfb_out_nc dif_in dif_in# oe(8,6,4,2)#
9ZXL1230 12-output low power differential buffer for pcie gen3 and qpi idt? 12-output low power differential buffer for pcie gen3 and qpi 2 9ZXL1230 rev b 041112 pin configuration power management table functionality at power-up (pll mode) power connections vdda dif_11# dif_11 dif_10# dif_10 gnd vdd vddio dif_9# dif_9 voe8# dif_8# dif_8 vddio 56 55 54 53 52 51 50 49 48 47 46 45 44 43 gn da 1 42 gnd nc 241 dif_7# 100m_133m# 340 dif_7 hibw_bypm_lobw# 439 voe6# ckpwrgd_pd# 538 dif_6# gnd 6 37 dif_6 vddr 736 gnd dif_in 835 vdd dif_in# 934 dif_5# smb_a0_tri 10 33 dif_5 smbdat 11 32 voe4# smbclk 12 31 dif_4# smb_a1_tri 13 30 dif_4 dfb_out_nc# 14 29 gnd 15 16 17 18 19 20 21 22 23 24 25 26 27 28 dfb_out_nc dif_0 dif_0# dif_1 dif_1# gnd vdd vddio dif_2 dif_2# voe2# dif_3 dif_3# vddio note: pins with ^ prefix have internal 120k pullup pins with v pref ix have internal 120k pulldowm 9ZXL1230 ckpwrgd_pd# dif_in/ dif_in# sm bus en bit dif(11:0)/ dif(11:0)# pll state if not in bypass mode 0xxlow/lowoff 0low/lowon 1 running on running 1 100m_133m# dif_in mhz dif(11:0) 1 100.00 dif_in 0 133.33 dif_in vdd vddio gnd 56 1 analo g pll 7 6 analog input 21,35,50 22,28,43,49 20,29,36,42, 51 dif clocks pin number description
9ZXL1230 12-output low power differential buffer for pcie gen3 and qpi idt? 12-output low power differential buffer for pcie gen3 and qpi 3 9ZXL1230 rev b 041112 pll operating mode readback table tri-level input thresholds pll operating mode 9ZXL1230 smbus addressing hibw_bypm_lobw# byte0, bit 7 byte 0, bit 6 low (low bw) 0 0 mid (bypass) 0 1 high (high bw) 1 1 level voltage low <0. 8v mid 1.2 2.2v hibw_bypm_lobw# mode low pll lo bw mid bypass high pll hi bw note: pll is off in bypass mode smb_a1_tri smb_a0_tri smbus address 0 0 d8 0 m da 01 de m 0 c2 m m c4 m1 c6 10 ca 1m cc 1 1 ce pi n
9ZXL1230 12-output low power differential buffer for pcie gen3 and qpi idt? 12-output low power differential buffer for pcie gen3 and qpi 4 9ZXL1230 rev b 041112 pin descriptions pin # pin na me type description 1 gnda pwr ground pin for the pll core. 2 nc n/a n o conn ection . 3 100m_133m# in 3.3v input to select operating frequency see functionality table for definit ion 4 hi bw_bypm_ lobw# in trilevel input to select high bw, bypass or low bw mode. see pll operating mode table for d etails. 5ckpwrgd_pd# in n otifies device to sample latched inputs and start up on first high assertion, or exit power down mode on subsequent assertions. low enters power down mode. 6 gnd pwr ground pin. 7vddr pwr 3.3v power for differential input clock (receiver). this vdd should be treated as an analog power rail and f iltered appropriately. 8 dif_in in 0.7 v differential true input 9 dif_in# in 0.7 v differential com p lementar y in p ut 10 smb_a0_tri in smbus address bit. this is a tri-level input that w orks in conjunction with the smb_a1 to decode 1 of 9 smbus addresses. 11 smbdat i/o d ata p in of sm bus circuitr y , 5v tolerant 12 smbclk in clock p in of smbu s circuitr y , 5v tolerant 13 smb_a1_tri in smbus address bit. this is a tri-level input that w orks in conjunction with the smb_a0 to decode 1 of 9 smbus addresses. 14 dfb_out_nc# out c omplementary half of differential feedback output, provides feedback signal to the pll for synchronization w ith input clock to eliminate phase error. this pin should not be connected on the circuit board, t he feedback is internal t o the p acka g e. 15 dfb_out_nc out true half of differential feedback output, provides feedback signal to the pll for synchronization with the input clock to eliminate phase error. this pin should not be connected on the circuit board, the feedback is internal t o the p acka g e. 16 dif_0 out 0.7v differential true clock output 17 dif_0# out 0.7v differential complementary clock output 18 dif_1 out 0.7v differential true clock output 19 dif_1# out 0.7v differential complementary clock output 20 gnd pwr ground pin. 21 vdd pwr power supply, nominal 3.3v 22 vddio pwr power supply for differential out puts 23 dif_2 out 0.7v differential true clock output 24 dif_2# out 0.7v differential complementary clock output 25 oe2# in active low input for enabling dif pair 2. 1 =disable out p uts, 0 = enable out p uts 26 dif_3 out 0.7v differential true clock output 27 dif_3# out 0.7v differential complementary clock output 28 vddio pwr power supply for differential out puts 29 gnd pwr ground pin. 30 dif_4 out 0.7v differential true clock output 31 dif_4# out 0.7v differential complementary clock output
9ZXL1230 12-output low power differential buffer for pcie gen3 and qpi idt? 12-output low power differential buffer for pcie gen3 and qpi 5 9ZXL1230 rev b 041112 pin descriptions (cont.) 32 oe4# in active low input for enabling dif pair 4 1 =disable out p uts, 0 = enable out p uts 33 dif_5 out 0.7v differential true clock output 34 dif_5# out 0.7v differential complementary clock output 35 vdd pwr power supply, nominal 3.3v 36 gnd pwr ground pin. 37 dif_6 out 0.7v differential true clock output 38 dif_6# out 0.7v differential complementary clock output 39 oe6# in active low input for enabling dif pair 6. 1 =disable outputs, 0 = enable outputs 40 dif_7 out 0.7v differential true clock output 41 dif_7# out 0.7v differential complementary clock output 42 gnd pwr ground pin. 43 vddio pwr power supply for differential out puts 44 dif_8 out 0.7v differential true clock output 45 dif_8# out 0.7v differential complementary clock output 46 oe8# in active low input for enabling dif pair 8. 1 =disable outputs, 0 = enable outputs 47 dif_9 out 0.7v differential true clock output 48 dif_9# out 0.7v differential complementary clock output 49 vddio pwr power su pp l y for differential out p uts 50 vdd pwr power su pp l y , nominal 3.3v 51 gnd pwr ground p in. 52 dif_10 out 0.7v differential true clock out p ut 53 dif_10# out 0.7v differential com p lementar y clock o ut p ut 54 dif_11 out 0.7v differential true clock out p ut 55 dif_11# out 0.7v differential com p lementar y clock o ut p ut 56 vdda pwr 3.3v power for the pll core.
9ZXL1230 12-output low power differential buffer for pcie gen3 and qpi idt? 12-output low power differential buffer for pcie gen3 and qpi 6 9ZXL1230 rev b 041112 absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the 9ZXL1230. these ratings, which are standard values for idt commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for ex tended periods can affect product reliability. electrical pa rameters are guaranteed only over the recommended operating temperature range. electrical characteristi cs?clock input parameters parameter symbol conditions min typ max units notes 3.3v core supply voltage v dd, vdd a vdd for core logic and pll 4.6 v 1,2 io supply voltage vdd_io vdd for differential io 4.6 v 1,2 input low voltage v il gnd-0.5 v 1 input high voltage v ih except for smbus interface v dd +0.5v v 1 input high voltage v ihsmb smbus clock and data pins 5.5v v 1 storage temperature ts -65 150 c 1 junction temperature tj 125 c 1 input esd protection esd prot human body model 2000 v 1 1 guaranteed by desi g n and characterization, not 100% tested in production. 2 operation under these conditions is neither implied nor g uaranteed. t a = t com ; supply voltage v dd = 3.3 v +/-5%, vdd_io = 1.05 to 3.3v +/-5% parameter symbol conditions min typ max units notes input high voltage - dif_in v i hdif differential inputs (sin g le-ended measurement) 600 800 1150 mv 1 input low voltage - dif_in v ildif differential inputs (single-ended measurement) v ss - 300 0 300 mv 1 input common mode volta g e - dif_in v com common mode input voltage 300 1000 mv 1 input amplitude - dif_in v swing peak to peak value 300 1450 mv 1 input slew rate - dif_in dv/dt measured differentially 0.4 8 v/ns 1,2 input leakage current i in v in = v dd , v in = gnd -5 5 ua 1 input duty cycle d tin measurement from differential wavefrom 45 55 % 1 input jitter - cycle to cycle j di fi n differential measurement 0 125 ps 1 1 guaranteed by desi g n and characterization, not 100% tested in production. 2 slew rate measured through +/-75mv window centered around differential zero
9ZXL1230 12-output low power differential buffer for pcie gen3 and qpi idt? 12-output low power differential buffer for pcie gen3 and qpi 7 9ZXL1230 rev b 041112 electrical characteristics?input/ supply/common output parameters t a = t com ; supply voltage v dd = 3.3 v +/-5%, vdd_io = 1.05 to 3.3v +/-5% parameter symbol conditions min typ max units notes ambient operating temperature t com commmercial range 0 70 c 1 input high voltage v ih single-ended inputs, except smbus, low threshold and tri-level inputs 2v dd + 0.3 v 1 input low voltage v il single-ended inputs, except smbus, low threshold and tri-level inputs gnd - 0.3 0.8 v 1 i in single-ended inputs, v in = gnd, v in = vdd -5 5 ua 1 i inp single-ended inputs v in = 0 v; inputs with internal pull-up resistors v in = vdd; inputs with internal pull-down resistors -200 200 ua 1 f ib yp v dd = 3.3 v, bypass mode 33 150 mhz 2 f i p ll v dd = 3.3 v, 100mhz pll mode 90 100.00 110 mhz 2 f i p ll v dd = 3.3 v, 133.33mhz pll mode 120 133.33 147 mhz 2 pin inductance l p in 7nh1 c in logic inputs, except dif_in 1.5 5 pf 1 c indif_in dif_in differential clock inputs 1.5 2.7 pf 1,4 c out output pin capacitance 6 pf 1 clk stabilization t stab from v dd power-up and after input clock stabilization or de-assertion of pd# to 1st clock 1ms1,2 input ss modulation frequency f modi n allowable frequency (triangular modulation) 30 33 khz 1 oe# latency t latoe# dif start after oe# assertion dif stop after oe# deassertion 412cycles1,3 tdrive_pd# t drvpd dif output enable after pd# de-assertion 300 us 1,3 tfall t f fall time of control inputs 10 ns 1,2 trise t r rise time of control inputs 10 ns 1,2 smbus input low voltage v ilsmb 0.8 v 1 smbus input high voltage v ihsmb 2.1 v ddsmb v1 smbus output low voltage v olsmb @ i pullup 0.4 v 1 smbus sink current i pullup @ v ol 4ma1 nominal bus voltage v ddsmb 3v to 5v +/- 10% 2.7 5.5 v 1 sclk/sdata rise time t rsmb (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata fall time t fsmb (min vih + 0.15) to (max vil - 0.15) 300 ns 1 smbus operating frequency f maxsmb maximum smbus operating frequency 100 khz 1,5 1 guaranteed by design and characterization, not 100% tested in production. 2 control input must be monotonic from 20% to 80% of input swing. 5 the differential input clock must be running for the smbus to be active input current 3 time from deassertion until outputs are >200 mv 4 dif_in input capacitance input frequency
9ZXL1230 12-output low power differential buffer for pcie gen3 and qpi idt? 12-output low power differential buffer for pcie gen3 and qpi 8 9ZXL1230 rev b 041112 electrical characteristics?dif 0.7v low power differential outputs electrical characterist ics?current consumption t a = t com ; supply voltage v dd = 3.3 v +/-5%, vdd_io = 1.05 to 3.3v +/-5% parameter symbol conditions min typ max units notes slew rate trf scope avera g in g on 1 3.3 4 v/ns 1, 2, 3 slew rate matching trf slew rate matching, scope averaging on 7 20 % 1, 2, 4 voltage high vhigh 660 778 850 1 voltage low vlow -150 0 150 1 max voltage vmax 985 1150 1 min voltage vmin -300 -91 1 vswing vswing scope averaging off 300 1556 mv 1, 2 crossin g volta g e (abs) vcross_abs scope avera g in g off 300 458 550 mv 1, 5 crossing voltage (var) -vcross scope averaging off 17 140 mv 1, 6 2 measured from differential waveform 6 the total variation of all vcross measurements in any particular system. note that this is a subset of vcross_min/max (vcross absolute) allowed. the intent is to limit vcross induced modulation by setting -vcross to be smaller than vcross absolute. mv statistical measurement on single-ended signal using oscilloscope math function. (scope averaging on) measurement on single ended signal using absolute value. (scope averaging off) mv 1 guaranteed by design and characterization, not 100% tested in production. c l = 2pf with r s = 33 ? for zo = 50 ? (100 ? differential trace impedance). 3 slew rate is measured through the vswing voltage range centered around differential 0v. this results in a +/-150mv window arou nd differential 0v. 4 matching applies to rising edge rate for clock and fa lling edge rate for clock#. it is measured using a +/-75mv window centered on the average cross point where clock rising meets clock# falling. the median cross point is used to calculate the voltage thresh olds the oscilloscope is to use for the edge rate calculations. 5 vcross is defined as voltage where clock = clock# measured on a component test board and only applies to the differential risi ng edge (i.e. clock rising and clock# fa lling). t a = t com ; supply voltage v dd = 3.3 v +/-5%, vdd_io = 1.05 to 3.3v +/-5% parameter symbol conditions min typ max units notes i ddvdd 133mhz, c l = full load; vdd rail 18 25 ma 1 i ddvdda 133mhz, c l = full load; vdda+vddr rail 16 20 ma 1 i ddvddi o 133mhz, c l = full load; vdd io rail 101 106 ma 1 i ddvddpd power down, vdd rail 0.01 1ma1 i ddvddapd power down, vdda+vddr rail 3 5ma1 i ddvddi opd power down, vdd_io rail 0.01 0.2 ma 1 1 guaranteed by desi g n and characterization, not 100% tested in production. operating current powerdown current
9ZXL1230 12-output low power differential buffer for pcie gen3 and qpi idt? 12-output low power differential buffer for pcie gen3 and qpi 9 9ZXL1230 rev b 041112 electrical characteristics?skew and differential jitter parameters t a = t com ; supply voltage v dd = 3.3 v +/-5%, vdd_io = 1.05 to 3.3v +/-5% parameter symbol conditions min typ max units notes clk_in, dif[x:0] t spo_pll input-to-output skew in pll mode nominal value @ 25c, 3.3v -100 -60 100 ps 1,2,4,5,8 clk_in, dif[x:0] t pd_byp input-to-output skew in bypass mode nominal value @ 25c, 3.3v 2.5 3.2 4.5 ns 1,2,3,5,8 clk_in, dif[x:0] t dspo_pll input-to-output skew varation in pll mode across volta g e and temperature -50 0 50 ps 1,2,3,5,8 clk_in, dif[x:0] t dspo_byp input-to-output skew varation in bypass mode across voltage and temperature -250 250 ps 1,2,3,5,8 clk_in, dif[x:0] t dte random differential tracking error beween two 9zx devices in hi bw mode 35 ps (rms) 1,2,3,5,8 clk_in, dif[x:0] t dsste random differential spread spectrum tracking error beween two 9zx devices in hi bw mode 10 75 ps 1,2,3,5,8 dif{x:0] t skew_all output-to-output skew across all outputs (common to bypass and pll mode) 60 65 ps 1,2,3,8 pll jitter peaking j p eak-hibw lobw#_bypass_hibw = 1 0 1.2 2.5 db 7,8 pll jitter peaking j p eak-lobw lobw#_bypass_hibw = 0 0 0.76 2 db 7,8 pll bandwidth pll hi bw lobw#_bypass_hibw = 1 2 3 4 mhz 8,9 pll bandwidth pll lobw lobw#_bypass_hibw = 0 0.7 1.1 1.4 mhz 8,9 duty cycle t d c measured differentially, pll mode 45 50.1 55 % 1 duty cycle distortion t dcd measured differentially, bypass mode @100mhz -2 0 2 % 1,10 pll mode 34 50 ps 1,11 additive jitter in bypass mode 17 50 ps 1,11 notes for preceding table: 6. t is the period of the input clock 7 measured as maximum pass band gain. at frequencies within the loop bw, highest point of magnification is called pll jitter pe aking. 8. guaranteed by design and characterization, not 100% tested in production. 9 measured at 3 db down or half power point. 10 duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in by pass mode. 11 measured from differential waveform 3 all bypass mode input-to-output specs refer to the timing between an input edge and the specific output edge created by it. 4 this parameter is deterministic for a given device 5 measured with scope averaging on to find mean value. jitter, cycle to cycle t jcyc-cyc 1 measured into fixed 2 pf load cap. input to output skew is measured at the first output edge following the corresponding inp ut. 2 measured from differential cross-point to differential cross-point. this parameter can be tuned with external feedback path, if present.
9ZXL1230 12-output low power differential buffer for pcie gen3 and qpi idt? 12-output low power differential buffer for pcie gen3 and qpi 10 9ZXL1230 rev b 041112 electrical characteristi cs?phase jitter parameters t a = t com ; supply voltage v dd = 3.3 v +/-5%, vdd_io = 1.05 to 3.3v +/-5% parameter symbol conditions min typ max units notes t jp hpcieg1 pcie gen 1 34 86 ps (p-p) 1,2,3 pcie gen 2 lo band 10khz < f < 1.5mhz 1.2 3 ps (rms) 1,2 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 2.2 3.1 ps (rms) 1,2 t jphpcieg3 pcie gen 3 (pll bw of 2-4mhz, cdr = 10mhz) 0.5 1 ps (rms) 1,2,4 qpi & smi (100mhz or 133mhz, 4.8gb/s, 6.4gb/s 12ui) 0.24 0.5 ps (rms) 1,5 qpi & smi (100mhz, 8.0gb/s, 12ui) 0.14 0.3 ps (rms) 1,5 qpi & smi (100mhz, 9.6gb/s, 12ui) 0.12 0.2 ps (rms) 1,5 t jp hpcieg1 pcie gen 1 3.7 10 ps (p-p) 1,2,3 pcie gen 2 lo band 10khz < f < 1.5mhz 0.1 0.1 ps (rms) 1,2,6 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 0.4 0.5 ps (rms) 1,2,6 t jphpcieg3 pcie gen 3 (pll bw of 2-4mhz, cdr = 10mhz) 0.09 0.2 ps (rms) 1,2,4,6 qpi & smi (100mhz or 133mhz, 4.8gb/s, 6.4gb/s 12ui) 0.14 0.1 ps (rms) 1,5,6 qpi & smi (100mhz, 8.0gb/s, 12ui) 0.01 0.1 ps (rms) 1,5,6 qpi & smi (100mhz, 9.6gb/s, 12ui) 0.01 0.1 ps (rms) 1,5,6 1 applies to all outputs. 6 for rms figures, additive jitter is calculated by solving the following equation: (additive jitter)^2 = (total jittter)^2 - (i nput jitter)^2 4 subject to final radification by pci sig. 5 calculated from intel-supplied clock jitter tool v 1.6.3 2 see http://www.pcisig.com for complete specs t jphpcieg2 t jphqpi_smi 3 sample size of at least 100k cycles. this figures extrapolates to 108ps pk-pk @ 1m cycles for a ber of 1-12. t jphqpi_smi 4 dif_in input t jphpcieg2
9ZXL1230 12-output low power differential buffer for pcie gen3 and qpi idt? 12-output low power differential buffer for pcie gen3 and qpi 11 9ZXL1230 rev b 041112 clock periods?differential outputs with spread spectrum disabled clock periods?differential outputs with spread spectrum enabled 1 cl ock 1us 0.1s 0.1s 0.1s 1us 1 clock -c2c jitter -ssc sh - ppm l 0 ppm period nominal + ppm l +ssc sh +c2 c jitter 100.00 9.94900 9.99900 10.00000 10.00100 10.05100 ns 1,2,3 133.33 7.44925 7.49925 7.50000 7.50075 7.55075 ns 1,2,4 ssc off center freq. mh z dif measurement window units notes 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock -c2c jitter absper min -ssc short-term average min - ppm long-term average min 0 ppm period nominal + ppm long-term average max +ssc short-term average ma x +c2 c jitter absper max 99.75 9.94906 9.99906 10.02406 10.02506 10.02607 10.05107 10.10107 ns 1,2,3 133.00 7.44930 7.49930 7.51805 7.51880 7.51955 7.53830 7.58830 ns 1,2,4 notes: 1 guaranteed b y desi g n and characterization, not 100% tested in p roduction. 3 driven b y src out p ut of main clock, 100 mhz pll mode or b yp ass mode 4 driven b y cpu out p ut of main clock, 133 mhz pll mode or b yp ass mode measurement window units ssc on center freq. mh z 2 all long term accuracy specifications are guaranteed with the assumption that the input clock complies with ck420bq/ck410b+ acc uracy requirements (+/-100ppm). the 9ZXL1230 itself does not contribute to ppm error. dif notes differential output terminations dif zo ( ? )rs ( ? ) 100 33 85 27 85ohm differential zo low-power hcsl- compatible output buffer 9zxl differential test loads rs rs 2pf 2pf 10 inches
9ZXL1230 12-output low power differential buffer for pcie gen3 and qpi idt? 12-output low power differential buffer for pcie gen3 and qpi 12 9ZXL1230 rev b 041112 general smbus serial interf ace information for 9ZXL1230 how to write ? controller (host) sends a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) sends the byte count = x ? idt clock will acknowledge ? controller (host) starts sending byte n through byte n+x-1 ? idt clock will acknowledg e each byte one at a time ? controller (host) sends a stop bit how to read ? controller (host) will send a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) will send a separate start bit ? controller (host) sends the read address ? idt clock will acknowledge ? idt clock will send the data byte count = x ? idt clock sends byte n+x-1 ? idt clock sends byte 0 through byte x (if x (h) was written to byte 8) ? controller (host) will need to acknowledge each byte ? controller (host) will send a not acknowledge bit ? controller (host) will send a stop bit index block write operation controller (host) idt (slave/receiver) tstart bit slave address wr write ack beginning byte = n ack data byte count = x ack beginning byte n x byte ack o o o o o o byte n + x - 1 ack pstop bit index block read operation controller (host) idt (slave/receiver) tstart bit slave address wr write ack beginning byte = n ack rt repeat start slave address rd read ack data byte count=x ack x byte beginning byte n ack o o o o o o byte n + x - 1 n not acknowledge pstop bit
9ZXL1230 12-output low power differential buffer for pcie gen3 and qpi idt? 12-output low power differential buffer for pcie gen3 and qpi 13 9ZXL1230 rev b 041112 smb ustable: pll mode, and frequency select re g ister pin # name control function t yp e 0 1 d efault bit 7 pll mode 1 pll operating mode rd back 1 r latch bit 6 pll mode 0 pll operating mode rd back 0 r latch bit 5 0 bit 4 0 bit 3 pll_sw_en enable s/w control of pll bw rw hw latch smbus control 0 bit 2 pll mode 1 pll o p eratin g mode 1 rw 1 bit 1 pll mode 0 pll o p eratin g mode 1 rw 1 bit 0 100m_133m# frequency select readbac k r 133mhz 100mhz latch smbustable: output control re g iste r pin # name control function type 0 1 default bit 7 dif_7_en out p ut control overrides oe# p in rw 1 bit 6 dif_6_en out p ut control overrides oe# p in rw 1 bit 5 dif_5_en out p ut control overrides oe# p in rw 1 bit 4 dif_4_en output control overrides oe# pin rw 1 bit 3 dif_3_en output control rw 1 bit 2 dif_2_en out p ut control rw 1 bit 1 dif_1_en out p ut control rw 1 bit 0 dif_0_en out p ut control rw 1 smbustable: output control re g iste r pin # name control function type 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 dif_11_en out p ut control rw 1 bit 2 dif_10_en out p ut control rw 1 bit 1 dif_9_en output control rw 1 bit 0 dif_8_en out p ut control rw 1 smb ustable: reserved register pin # name control function t yp e 0 1 d efault bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 smb ustable: reserved re g ister pin # name control function type 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 smb ustable: vendor & revision id r e g iste r pin # name control function type 0 1 default bit 7 rid3 r x bit 6 rid2 r x bit 5 rid1 r x bit 4 rid0 r x bit 3 vid 3 r - - 0 bit 2 vid 2 r - - 0 bit 1 vid 1 r - - 0 bit 0 vid 0 r - - 1 reserved reserved low/low enable reserved reserved reserved reserved reserved reserved reserved low/low enable reserved reserved reserved reserved reserved reserved reserved reserved reserved - - - - a rev = 0000 4 byte 1 42/41 55/54 23/24 18/19 byte 0 3 3 48/47 byte 3 46/45 53/52 25/26 byte 2 16/17 byte 5 byte 4 - - - - see pll operating mode readback table revision id reserved reserved ven dor id see pll operating mode readback table note: setting bit 3 to '1' allows the user to overide the latch value from pin 5 via use of bits 2 and 1. use the values from the pl l operating mode readback table. note that bits 7 and 6 will keep the value originally latched on pin 5. a warm reset of the system will have t o accomplished if the user changes these bits. reserved reserved 38/37 34/35 30/29
9ZXL1230 12-output low power differential buffer for pcie gen3 and qpi idt? 12-output low power differential buffer for pcie gen3 and qpi 14 9ZXL1230 rev b 041112 smb ustable: device id pin # name control function t yp e 0 1 d efault bit 7 r1 bit 6 r1 bit 5 r1 bit 4 r0 bit 3 r0 bit 2 r1 bit 1 r1 bit 0 r0 smbustable: byte count re g iste r pin # name control function type 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 bc4 rw 0 bit 3 bc3 rw 1 bit 2 bc2 rw 0 bit 1 bc1 rw 0 bit 0 bc0 rw 0 smb ustable: reserved re g ister pin # name control function type 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 device id 2 device id 1 device id 4 byte 8 - - - - - - - reserved - device id 3 - writing to this register configures how many bytes will be read back. device id 0 default value is 8 hex, so 9 bytes (0 to 8) will be read back by default. - reserved reserved reserved reserved reserved reserved reserved byte 7 - - - byte 6 reserved reserved 1230 is 230 d ecimal or e6 hex device id 7 (msb) reserved device id 5 device id 6
9ZXL1230 12-output low power differential buffer for pcie gen3 and qpi idt? 12-output low power differential buffer for pcie gen3 and qpi 15 9ZXL1230 rev b 041112 marking diagram notes: 1. ?lot? is the lot number. 2. yyww is the last two digits of the year and week that the part was assembled. 3. ?l? denotes rohs compliant package. 4. ?coo? denotes country of origin. ics 9ZXL1230al lot coo yyww
9ZXL1230 12-output low power differential buffer for pcie gen3 and qpi idt? 12-output low power differential buffer for pcie gen3 and qpi 16 9ZXL1230 rev b 041112 package outline and package dimensions (56-pin mlf) ordering information "lf" suffix to the part number are the pb -free configuration and are rohs compliant. ?a? is the device revision designator (will not correlate with th e datasheet revision). while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any paten ts or other rights of third parties, which would resul t from its use. no other circuits, patents, or licenses are im plied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliab ility, or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves th e right to change any circuitry or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments. part / order number marking shipping packaging package temperature 9ZXL1230aklf see page 15 trays 56-pin mlf 0 to +70 c 9ZXL1230aklft tape and reel 56-pin mlf 0 to +70 c millimeters symbol min max a0.81.0 a1 0 0.05 a3 0.25 reference b 0.18 0.3 e 0.50 basic d x e basic 8.00 x 8.00 d2 min./max. 4.35 4.65 e2 min./max. 5.05 5.35 l min./max. 0.30 0.50 n56 n d 14 n e 14 anvil singulation -- or -- sawn singulation 1 2 n e d index area top view seating plane a3 a1 c a l e2 e2 2 d2 d2 2 e c 0.08 (ref) n d & n e odd (ref) n d & n e even (n d -1)x (ref) e n 1 2 b thermal base (typ) if n d & n e are even (n e -1)x (ref) e e 2
9ZXL1230 12-output low power differential buffer for pcie gen3 and qpi idt? 12-output low power differential buffer for pcie gen3 and qpi 17 9ZXL1230 rev b 041112 revision history rev. issuer issue date description page # a rdw 12/8/2011 1. changed output features description 2. corrected title of smbus addressing table 3. updated tdspo_byp to +/-250ps and all electrical tables with typical values. idd specs revised downward. 4. updated differential test loads figure to indicate impedance and trace length. 5. removed smbus address info on page 12, smbus address is selectable as indicated on page 3. 6. mark spec added. 7. move to final 1,3,6- 10,11, 12,15 b rdw 4/11/2012 1. updated vdd and vddio pin numbers in the power connections table, pinout is correct. 2
? 2011 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt, ic s, and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa corporate headquarters integrated device technology, inc. www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support www.idt.com/go/clockhelp pcclockhelp@idt.com innovate with idt and accelerate your future netw orks. contact: www.idt.com 9ZXL1230 12-output low power differ ential buffer for pcie gen3 and qpi synthesizers

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